The present invention relates generally to an integrator which is capable of continuous integration while allowing readout and reset functions, and more particularly to an integrator which is capable of integrating an input charge and enabling a readout and reset of the integrator without disconnecting the input charge from the input amplifier and without loosing any of the input charge during the readout and reset functions.
A computerized tomography (CT) scanner includes a highly stable X-ray beam generator that generates an X-ray beam that is focused on a specific plane of the body. As this beam passes through the body, it is picked up by a detector, which feeds the information it receives into a computer. The computer then analyzes the information on the basis of tissue density. This analyzed data is then fed into a cathode ray tube and a picture of the X-rayed, cross-section of the body is produced. Bone shows up as white; gases and liquids as black; and, tissue as varying shades of gray, depending on its density.
It is extremely important for the circuitry associated with the detector to collect and process all of the energy received by the detector to insure accurate scans. The devices that receive the energy as an input charge must be able to continuously integrate the input charge even during readout and reset functions, so that none of the input charge is unaccounted for. Shown in FIG. 1 is a prior art circuit 100 for integrating such an input charge. Circuit 100 includes a pair of integrators 102a and 102b in which one of the integrators collects the input charge Iin and processes it while the other integrator is read out from the previous integration and reset.
When conducting a CT scan, it is critical that the readings provided by the integrators be accurate to approximately 0.03%. However, it is virtually impossible to construct the capacitors 104a and 104b associated with the integrators 102a and 102b, respectively, to a tolerance that will allow the required accuracy. This results in differences in the offsets and gains of the integrators 102a and 102b with respect to each other. Accordingly, tables for each integrator must be constructed to correct for the differences in the offset and gain that result from inaccuracies in the construction of the components of the integrators, in particular the capacitors 104a and 104b. Utilization of such tables requires additional software for processing the collected charge and introduces undesired complexity to the circuit.
The present invention is directed to an integration device which is capable of continuously integrating an input charge while also allowing for readout and reset functions without losing any of the input charge. The device does not require more than a single set of correction tables, as the input charge is read out from a single capacitor.
According to one embodiment, an integration circuit includes an input node for receiving an input charge, an integrator including a first amplifier having an input terminal coupled to the input node, an output terminal and a first charge storage device coupled between the input and output terminals, an intermediate node coupled between the input node and ground, a second charge storage device having a first terminal coupled to the intermediate node and a second terminal coupled to an output node of the integration circuit, a first switch device coupled between the input node and the intermediate node; and a second switch device coupled between the output terminal of the integrator and the output node. During a first phase of operation, the first and second switch devices are open, and the input charge received on the input terminal of the integrator is stored on the first charge storage device. During a second phase of operation, the first and second switch devices are closed, and the charge stored on the first charge storage device is transferred to the second charge storage device.
The integration circuit may further include a third switch device coupled between the intermediate node and ground, wherein, during the first phase of operation, the third switch device is closed, and the charge stored on the second charge storage device is transferred to the output node of the integration circuit. The integration circuit may further include a fourth switch device coupled between the second terminal of the second charge storage device and ground, wherein, during a third phase of operation, the fourth switch device is closed, and the second charge storage device is discharged to ground. The integration circuit may further include a second amplifier coupled between the output terminal of the first amplifier and the second switch device. The first, second, third and fourth switch devices may include transistors. The first and second charge storage devices may include capacitors.
According to another embodiment, an integration circuit includes an input node for receiving an input charge, an integrator having an input terminal coupled to the input node, an output terminal and a first charge storage device coupled between the input and output terminals, an intermediate node coupled between the input terminal and ground, a second charge storage device having a first terminal coupled to the intermediate node and a second terminal coupled to an output node of the integration circuit and an isolation device coupled between the integrator and the second charge storage device for selectively isolating the integrator from the second charge storage device. During a first phase of operation, the isolation device is activated and isolates the integrator from the second charge storage device, and the input charge received on the input terminal of the integrator is stored on the first charge storage device. During a second phase of operation, the isolation device is deactivated and enables and the charge stored on the first charge storage device to be transferred to the second charge storage device.
During a first portion of the first phase of operation, a charge stored on the second charge storage device may be read out to the output node of the integration circuit. During a second portion of the first phase of operation, the second charge storage device may be discharged to ground. The integration circuit may further include means for selectively connecting the first terminal of the second charge storage device to ground during the first portion of the first phase of operation. The isolation device may include a first switch device coupled between the input node and the intermediate node and a second switch device coupled between the output terminal of the integrator and the output node. The means for selectively connecting the first terminal of the second charge storage device to ground may include a switch device coupled between the intermediate node and ground, wherein, during the first portion of the first phase of operation, the third switch device is closed, and the charge stored on the second charge storage device is transferred to the output node of the integration circuit. The means for selectively connecting the second terminal of the second charge storage device to ground may include a switch device coupled between the second terminal of the second charge storage device and ground, wherein, during the second portion of the first phase of operation, the fourth switch device is closed, and the second charge storage device is discharged to ground. The first and second charge storage devices may each include a capacitor.